Master's or Bachelor's degree in Electrical Engineering with emphasis in Design Verification or a similar specialty, as well as proven industry experience Expertise in block- and system-level verification with reusable components, testbench architecture and verification planning Experience with analog behavioral modelling with System Verilog RNM and Verilog-AMS Experience with relevant EDA tools and familiarity with scripting languages (e.g. Python, SKILL) Excellent team player; calm professional demeanor and excellent listening skills, ability to organize and prioritize work Fluency in English